AVAILABLE FOR ONE CONTRACT ENGAGEMENT

ANDREAS FALKENBERG — PHD

Compilers forcustom AIsilicon.

I put PyTorch and ONNX models onto bespoke accelerators — LLVM/MLIR lowering, graph partitioning and hardware-software co-design for AI-silicon teams.

RÉSUMÉ — PDF

SCROLL

LLVM//MLIR//PYTORCH//ONNX//CUSTOM BACKENDS//GRAPH PARTITIONING//QUANTIZATION//SYSTEMC//FPGA / HLS//KERNEL CODEGEN//HW-SW CO-DESIGN//

01 // WHAT I DO

Four ways I plug into your stack.

LLVM / MLIR Compiler Architecture

End-to-end compiler stacks for custom silicon: dialect design, pass pipelines, scheduling and codegen shaped around your hardware.

DIALECTSPASS PIPELINESCODEGENCOST MODELS

PyTorch / ONNX Lowering & Custom Backends

Bridging model graphs to your target: torch-mlir / ONNX lowering paths, custom backend integration, operator coverage and numerics that hold.

TORCH-MLIRONNXBACKEND HOOKSNUMERICS

Hardware-Aware Partitioning & Quantization

Making models fit the machine: partitioning across compute tiles, quantization and QAT strategy, memory-aware scheduling and tiling.

PARTITIONINGQUANT / QATTILINGMEMORY PLANNING

ASIC / SoC & FPGA, SystemC Co-Design

Working the hardware-software boundary: ISA and intrinsic feedback, SystemC performance models, FPGA bring-up and early compiler validation for SoC teams.

SYSTEMCFPGA BRING-UPISA FEEDBACKPERF MODELING

02 // EXPERIENCE

Named employers. Real hardware.

AMD / Xilinx

Ryzen AI

Upstream torch-mlir contributions and custom-backend work lowering ONNX/PyTorch models onto Ryzen AI NPUs — including NPU kernel integration and compiler validation.

BrainChip

Sole Compiler Engineer

Built the complete MLIR-based compiler stack for BrainChip's next-generation neuromorphic processor — from ONNX, PyTorch, and TensorFlow graph ingestion through custom dialect design, middle-end optimization passes (fusion, tiling, quantization, layout), custom ISA backend codegen, and runtime integration. Defined the correctness validation strategy and led a researcher to scale it to 800+ test cases.

d-Matrix

Inference silicon

Graph-to-hardware mapping for transformer inference on in-memory compute.

Metawave

Radar perception

Radar accuracy 69% → 95% — signal-chain ML taken from lab to field.

Ostendo

Photonic display

Designed the backend ASIC for a photonic embedded display from first principles through physical tapeout — architecture, RTL, and validation.

* SELECTED ENGAGEMENTS — FULL DETAIL IN THE RÉSUMÉ PDF

2×

PHD — DOCTORATES

PATENTS — 33 GRANTED

PEER-REVIEWED PUBLICATIONS

INVITED TALKS

UNIVERSITY COURSES

GOOGLE SCHOLAR LINKEDIN

04 // CONTACT

One engagement.
Let's make it count.

andreas@falkenbergtech.com

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